Converters, for example digital to analog converters (DAC's), can be calibrated to correct linearity errors through mixed-signal analog solutions with correction DACs to compensate for random and systematic errors. In that approach the output of the primary DAC is compared with a reference or ideal output. A difference between the two results in a signal being delivered to a correction DAC to cause it's output to drive the difference toward zero. While this approach effects a reduction of the error, it introduces other shortcomings. It requires a mixed signal solution using analog and digital components which add to the complexity. Further, the two DACs must be closely monitored so that conditions will affect both DAC's similarly e.g. both have the same changes in response to a change in temperature. It also results in a larger system due to interconnects and partitioning of the design. The same problems exist for analog to digital converters (ADC's).
One typical prior art system for compensating for digital to analog converter errors is shown in FIG. 9, where the primary DAC 90 is accompanied by a correction DAC 92, a comparator 94, summing circuit 96 and SAR (Successive Approximation Register) logic 98. In operation, the output of DAC 90 is compared to an ideal reference by comparator 94. The SAR logic provides an input to correction DAC 92 drive summing circuit 96 to minimize the difference sensed by comparator 94. The output of DAC 92 is summed with the output of DAC 90 in summer 96 and delivered back to comparator 94. As indicated earlier in the background one of the problems with this approach is that DACs 92 and 90 must be matched so that they respond similarly to the same conditions, e.g. process, voltage, temperature (PVT). In addition there is the expense and complexity of the added DAC and its associated circuitry. This also employs a mixed signal approach which increases complexity and cost.
U.S. Pat. No. 6,292,125 discloses a system and method for digital-to-analog conversion which provides an accurate and reliable digital-to-analog conversion. The system discloses a DAC comprising a plurality of analog weight having associated digital sizes. The conversion works by receiving a binary input, searching for selected weights from the analog weights, which has an associated digital size, then outputs a sum of the selected analog weights. A problem with this U.S. patent is that the architecture is constrained by using elements of differing weights. Using different sizes is widely known as a bad practice, to those skilled in the art, for matching purposes. This constraint results in degradation of second order effects e.g. temperature & voltage coefficient mismatch, which are also important on high performance designs. There may also be a large memory requirement to store weights for each element and this is especially true for architectures with many contributing elements e.g. string DACs with 2N elements or as that disclosed in another document U.S. Pat. No. 5,969,657 which makes the weight table of the converter excessively large and complex. The mapping of the weights also becomes more complex.
Another U.S. Pat. No. 6,456,112 discloses a system for calibrating data converters which uses pre-digital error correction codes, which directly reflect the behaviour of each stage of an analog to digital converter. The system operates by providing one or more pre-digital error correction codes from the input signal which are compared to transition voltage expressions by using a 0 or 1 output to improve the accuracy and calibration of the analog to the digital converter. However a problem with this patent is that the error codes do not represent the complete error in the signal. Furthermore this system is specifically directed to compensating the error on the output digital signal of an analog to digital converter.